4 bit ALU with MIT's 0.25micron technology kit

The following is a report summarizing the first project for ECE4500 digital electronics at Western Michigan University.

Images for layouts and schematics follow at the end of the report.

Introduction

The purpose of this project is to design an ALU to perform certain operations with signed 2’s complement 4 bit numbers. The ALU uses an 8-1 MUX in order to select the output according to a 3-bit control signal S0-S2. The inputs are A0-A3 and B0-B3. The outputs are F0-F3.

Discussion

The 8-1 MUX is the core of the design, allowing different inputs to be selected depending on the control signals S0-S2. The following truth table demonstrates the actual outputs for the selected test signals as demonstrated in the project.

The parts were all built independently and used as components. Special care was taken to keep all voltage lines on the top and bottom of the component for VSS and VDD respectively. This allowed for consistent design methodology and a more compact final layout.

In the design of the individual components we were careful to not use metal 3 with limited use of metal 2. This allowed for easier routing of the whole ALU as these metal layers were available to cross most parts.

Function Tests:

These values were obtained using the Xelga simulator included in the Mentor Graphics design suite. The input values are those for the test file provided in the project requirements.

Command Inputs Output Flags
CC OP A B F C S Z OVF
000 A 1010 1011 1010 1 0 0
001 !A 1010 1011 0101 0 0 0
010 A&B 1010 1011 1010 1 0 0
011 A#B 1010 1011 1011 1 0 0
100 A$B 1101 1011 0110 0 0 0
101 A+B 1101 1011 1000 1 1 0 0
110 A-B 1101 1011 0010 1 0 0 0
111 B 1101 1011 1011 1 0 0

Flag Tests:

These values were obtained using the Xelga simulator for Mentor Graphics, as well. The input values are those for the test file provided in the project requirements to test the outputs of the flags.

Command Inputs Output Flags
CC OP A B F C S Z OVF
110 A-B 1110 1110 0000 1 0 1 0
101 A+B 1001 1010 0011 1 0 0 1

Performance Values for individual components:

NOT AND XOR
Wp (um) 5.0 Wp (um) 5.0 Wp (um) 5.0
Lp (um) 1.2 Lp (um) 1.2 Lp (um) 1.2
Wn (um) 2.0 Wn (um) 2.0 Wn (um) 2.0
Ln (um) 1.2 Ln (um) 1.2 Ln (um) 1.2
Tplh (ps) 35 Tplh (ps) 37 Tplh (ps) 36.8
Tphl (ps) 34.1 Tphl (ps) 41.2 Tphl (ps) 22.3
Full Adder MUX8 Zero
Wp (um) 5.0 Wp (um) 2.0 Wp (um) 5
Lp (um) 1.2 Lp (um) 1.2 Lp (um) 1.2
Wn (um) 2 Wn (um) 4 Wn (um) 2
Ln (um) 1.2 Ln (um) 1.2 Ln (um) 1.2
Tplh (ps) 141 Tplh (ps) 1050 Tplh (ps)
Tphl (ps) 147 Tphl (ps) 269 Tphl (ps) 46.6

Overall circuit performance:

The maximum tplh and tphl are caused by the ripple carry adder circuit. The values are as follows:


tplh = 6.46 ns
tphl = 6.60 ns
tp = 6.53 ns
A^2 = 177 * 161.4 = 28567.8 u^2
using a 0.25 micron process size:
A^2 = (177 * 0.25e-6) * (161.4 * 0.25e-6) = 1.785nm^2

These values are within an acceptable range for the process size and technology.

Transistor counts

The total transistor count is 280. This value is broken up as follows:

Component # of components # of transistors in each component Total # of transistors from this component
NOT 15 2 30
AND2 7 4 28
OR2 5 4 20
XOR2 5 4 20
NAND2 3 4 12
NAND3 1 6 6
MUX2 4 4 16
MUX8 4 17 68
ZERO 1 8 8
FULL_ADDER 4 18 72
Total: 49 280

Conclusion:

A variety of design styles were used, including static CMOS, pass transistor, and transmission gate logic. static CMOS proved effective for the simple logic gates. Pass transistor logic allowed for much smaller and faster multiplexers. Transmission gates allowed for good output levels, and smaller design for several components including the full adder. Level restorers were used on the ends of the final multiplexers, allowing for future use of the ALU as a whole.

The circuit performs as expected, and the performance values exceed expectations. This project has demonstrated methods to design more complex components, and has helped develop effective strategies to design these components.

Image: 
ALU Schematic
ALU Layout
AND2 Schematic
AND2 Layout
Full Adder Schematic
Full Adder Layout
MUX2 Schematic
MUX2 Layout
MUX8 Schematic
MUX8 Layout
NAND2 Schematic
NAND2 Layout
NAND3 Schematic
NAND3 Layout
NOT Schematic
NOT Layout
OR2 Schematic
OR2 Layout
XOR Schematic
XOR2 Layout
Zero Detector Schematic
Zero Detector Layout
ALU functional waves
ALU flag waves
ALU worst case tPHL
ALU worst case tPLH
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